1. Field of the Invention
The present invention relates to a method of manufacturing a borderless contact hole. More particularly, the present invention relates to a method of manufacturing a borderless contact hole having low resistance.
2. Description of the Related Art
With the decrease of wire width in ICs and the increase of integration of ICs, the size of a contact in a device becomes small. Hence, it is more difficult to align a contact hole site with the contact of the device. When misalignment occurs as the dielectric layer is patterned to form a contact hole, the etching step used to form the contact hole may damage the isolation structure between devices. Therefore, the leakage happens.
In order to overcome the problem mentioned above, the method for manufacturing a borderless contact hole has been developed. Typically, method for manufacturing the borderless contact hole comprises the steps of forming an etching stop layer over a substrate and devices. An inter-layer dielectric (ILD) layer is formed on the etching stop layer. The ILD layer is patterned to expose a portion of the etching stop layer. The exposing etching stop layer is removed to form a contact hole. When misalignment happens, the etching stop layer can resist the continuation of the etching step, so that the isolation structure or the spacer adjacent to the contact of the device can be prevented by the etching stop layer. Therefore, the quality of the device can be maintained. As the wire width in ICs gradually decrease to 0.25 micrometers, or even below 0.25 micrometers, borderless contact hole structure is used instead of the conventional contact hole.
FIGS. 1A through 1C are schematic, cross-sectional views of a process for manufacturing a borderless contact hole.
As shown in FIG. 1A, a pad oxide layer 102 is formed on a substrate 100. A silicon nitride layer 104 is formed on the pad oxide layer 102. A trench 106 is formed to penetrate through the silicon nitride layer 104 and the pad oxide layer 102 and into the substrate 100. An oxide layer 108 is formed to fill the trench 106. A planarizing step is performed to remove a portion of the oxide layer 108 and silicon nitride layer 104 and to form a shallow trench isolation (STI) 110.
As shown in FIG. 1B, the silicon nitride layer 104 and the pad oxide layer 102 are removed. Since the material of the STI 110 is similar to that of the pad oxide layer, the surface level of the STI is almost equal to that of the substrate 100 after the pad oxide layer 102 is removed. A transistor 130 having a gate oxide layer 112, a gate electrode 114, a spacer 116 and a source/ drain region 118 is formed on the substrate 100 adjacent to the STI 110.
As shown in FIG. 1C, a salicide process is performed to form a silicide layer 120 on the gate electrode 114 and the surface of the source/drain region 118. An etching stop layer 122 is formed over the substrate 100. A dielectric layer 124 is formed on the etching stop layer 122. When misalignment happens during contact hole 126 formation, contact hole 126 penetrates through the dielectric layer 124 and exposes a portion of the etching stop layer 122. The portion of the etching stop layer 122 exposed by the contact hole 126 is removed to expose a portion of the silicide layer 120 and the STI 110. Hence, the process for manufacturing the borderless contact hole is finished.
In the process for forming the borderless contact hole, although the isolation structure will not be damaged by the etching step when misalignment happens, the portion of the contact area exposed by the contact hole is greatly decreased. After a metal plug or a bit line is formed in the contact hole, the contact area is very small, so that the resistance between the metal plug or the bit line and the device increases. Therefore, the operation efficiency of the device is poor.